Computing power, now and next: a landscape map — where is the real bottleneck?

Evidence-first notes on bioscience and deep tech, at the edge of the lab and the market. Information only — not investment advice.

The 30-second version

• What. Computing-power debates compress into headline metrics (node nm, “N-times faster,” qubit counts, TB/s), but the step that actually blocks real use sits systematically next to those numbers. The landscape’s core finding: the real bottleneck is not silicon miniaturization.
• So what. Three bottlenecks recur. For AI compute it is grid interconnection (4–10 years), not chips or capital; for memory systems it is data movement, not compute; for silicon it is economics (rising cost-per-transistor), not physics. Miniaturization continues, but the binding constraint is elsewhere.
• Now what. Read every paradigm by actual TRL and the real bottleneck, not the headline metric. Post-CMOS candidates span TRL 9 (frontier CMOS) down to 2–4 (thermodynamic/reversible), and several efficiency multiples circulating in trade press are vendor/simulation claims that are not mutually comparable.

[demo-gap note] Read the post-CMOS field by evidence tier. Google’s Willow below-threshold result is real hardware but at the scale of one logical qubit and not a useful computation. Digital compute-near-memory (CNM) is commercialized, but analog in-memory (CIM) is a research prototype only. Thermodynamic/reversible efficiency multiples (e.g., “10,000x”) rest on vendor simulations and toy benchmarks, with no independent physical benchmark source secured.

The five-minute read

The through-line: the bottleneck is elsewhere

Computing power gets compressed into a few headline numbers, yet the rate-limiting step for real use consistently sits beside them. Frontier miniaturization has not stopped — TSMC’s N2 (2nm) uses GAA/nanosheet transistors and entered volume production in Q4 2025 — but the constraint that decides real-world throughput has moved off the transistor. The point of this map is to relocate the debate from “how small is the node?” to “what is the binding constraint, and where does it actually live?“

A domain-by-domain bottleneck map

Silicon: economics, not physics. Node names are marketing — “2nm” has no relation to a physical dimension (contacted gate pitch is ~45nm). Per-node gains keep shrinking (N2 offers roughly +10–15% iso-power performance, or −20–30% power, over N3E). The confirmed claim is that manufacturing cost is rising faster than density scaling, so the per-transistor cost decline has broken down [CONFIRMED, 2-1]. The stronger trade-press framing — that this is the “first-ever inflection” — is refuted: cost-per-transistor stagnation has been debated since roughly 28nm/finFET, so it is a cumulative trend, not a new event.

Memory: data movement, not compute. Moving data between logic and memory consumes 10–100x more energy than the logic operation itself [CONFIRMED, 3-0] — the memory wall. This is why compute-in/near-memory and HBM/advanced packaging became new scaling axes. HBM4 doubles the interface to 2,048-bit (~2 TB/s per stack), and CoWoS/HBM supply stays very tight through 2026, signaling that the AI bottleneck is packaging and HBM rather than logic wafers.

AI datacenters: the grid, not the chip. Frontier AI training compute roughly doubles every 5–6 months — by deploying larger chip clusters, not by miniaturization — so the constraint shifts from silicon efficiency to physical grid capacity. Grid interconnection takes 4–10 years while a datacenter is built in 2–3, making grid access the binding constraint. This is where the firm’s energy thread (reactors for AI power) meets its computing coverage.

[diagram: where the real bottleneck lives, by domain]

  DOMAIN                 HEADLINE METRIC        REAL BOTTLENECK (elsewhere)
  ───────────────────────────────────────────────────────────────────────
  Frontier CMOS (N2/A16) node nm / density  ->  cost-per-transistor, design cost
  Advanced packaging     TB/s / pitch       ->  CoWoS/HBM supply, yield, heat
  AI datacenters         FLOPs / clusters   ->  grid interconnection (4-10 yrs)
  In-memory (CIM/CNM)    energy efficiency  ->  programmability / SW ecosystem
  Quantum (QEC)          qubit count / Lambda -> magic state, physical overhead
  Photonic neuromorphic  speed-of-light MAC ->  E-O conversion, nonlinearity
  Neuromorphic           TOPS/W multiples   ->  SW ecosystem; sparse-only edge
  Superconducting SFQ    GHz clock          ->  cryogenic cooling (COP   absence of physical demonstration

Deep dive

1. Background — reading computing by bottleneck, not by headline

This is Part 0 of a planned deep-dive series: a map that sweeps the whole terrain through the firm’s three lenses (technical roadmap / commercialization overlay / skeptic), with later parts drilling into each sub-area. The organizing idea, drawn from the firm’s own cross-week synthesis on the “bottleneck fallacy,” is that computing-power progress is narrated through headline indicators while the actual rate-limiting step sits systematically beside them. Frontier scaling continues; the question is whether it is still the binding constraint. Across the domains below, it usually is not.

2. What this landscape newly establishes

Core finding: the real bottleneck of computing power is not silicon miniaturization. It is, respectively, grid interconnection (AI compute), data movement (memory), and economics (silicon) — and post-CMOS alternatives should be read by their honest TRL and their specific rate-limiter, not their headline.

• Silicon economics is the constraint — CONFIRMED (2-1): manufacturing cost rises faster than density gains, breaking the per-transistor cost decline. The “first-ever inflection” frame is REFUTED (0-3) — the debate predates this node, so it is a cumulative trend. Dennard scaling has ended (established physics): leakage grows to the same order as dynamic power, bounding threshold-voltage scaling.
• Data movement dominates energy — CONFIRMED (3-0): logic-to-memory transfer costs 10–100x more energy than the logic op itself (the von Neumann / memory wall). This reframes packaging and HBM as the new scaling axis.
• Digital CNM is commercial; analog CIM is not — CONFIRMED (3-0): near-bank/near-memory DPUs and PIM (UPMEM, Samsung, SK Hynix) ship, but analog crossbar CIM (e.g., RRAM) remains an academic prototype (device non-idealities, drift, slow writes). Do not blur “in-memory” — digital CNM (commercial) and analog CIM (research) are different maturity tiers. And the real bottleneck for both is programmability / the software ecosystem, not device physics [CONFIRMED, 3-0].
• Grid access binds AI compute — [WEF, secondary/high]: training compute doubles every 5–6 months via larger clusters; grid interconnection (4–10 yrs) versus datacenter build (2–3 yrs) makes the power system, not chips or capital, the binding constraint. This connects directly to nuclear (SMR/microreactor) as dedicated datacenter power — inheriting that thread’s skeptic caveat: criticality is not commercial generation, and HALEU fuel is the bottleneck.

3. Strengths and limits of the evidence

Strengths: primary-source anchors exist for the two highest-leverage claims — the memory wall (arXiv 2401.14428, primary/high) and quantum error-correction below threshold (Nature, Google Willow, primary/high) — and adversarial verification killed two trade-press exaggerations (the “first-ever cost inflection” and the “2nm >50% over 3nm” wafer-cost framing). Limits: several commercialization figures are vendor/blog projections requiring attribution — for example, the D2W hybrid-bonding market CAGR (~57%) is a vendor projection [blog/low], and dark-silicon percentages come from a 2014 IEDM projection, not measurement, so they indicate direction only. Grid-timeline and capacity figures are secondary/high but region-dependent. The verdict table below mixes extracted claims with author judgment on TRL and outlook.

4. Neighbouring domains

Two non-forced connections hold. First, energy: AI compute power demand drives the nuclear revival, which the firm covers on its energy axis — so from a general-investor vantage, computing, energy and semiconductor materials bind into one logic chain. Second, quantum: the firm’s logical-Clifford compiler thread meets this map’s post-CMOS section, where theory/compiler progress is explicitly separated from hardware demonstration (magic state remains the bottleneck). No forced CKM (cardio-renal-metabolic) hook is asserted — compute is upstream infrastructure to AI-driven biology, but even there the bio bottleneck is data and validation (wet-lab, clinical), not FLOPs, so the “bottleneck is elsewhere” pattern repeats one layer up.

5. Commercialization and market context (TRL, companies)

Company context (factual, neutral, no buy/sell implication): frontier logic and packaging concentrate on a few nodes — TSMC logic, the three HBM makers (SK Hynix, Samsung, Micron, all US-allied), ASML EUV, and CoWoS capacity. Post-CMOS players by modality include IBM, Google and SeeQC (superconducting/SFQ), Intel and IBM (neuromorphic: Loihi 2 / NorthPole), UPMEM, Samsung and SK Hynix (commercialized digital CNM), and Extropic and Normal Computing (thermodynamic, private). Vendor efficiency multiples (10,000x / 1,000x / 25x / 72.7x / 15 TOPS·W) rest on differing assumptions (sparsity ratio, benchmark type, comparison GPU generation) and are not mutually comparable — always cite the premise. Vendor roadmap dates are attributed as projections.

6. The skeptic’s bottom line

• Adversarial verification complete (9 synthesized findings confirmed, 2 killed, 0 unverified across 111/111 agents). Two trade-press exaggerations were killed: the “first-ever cost-per-transistor inflection” (refuted 0-3) and the “2nm wafer >50% over 3nm” framing (refuted 0-3 — absolute ~$30k confirmed, but the baseline was ~$25–27k, not $20k, so the increase is overstated).
• demo-gap: Willow is real hardware but one logical qubit and not a useful computation, and its own authors state it is “not yet fault-tolerant computation.” Analog CIM, photonic and thermodynamic results are heavily prototype/simulation. Thermodynamic multiples come from vendor simulations plus toy benchmarks (e.g., Fashion-MNIST), with no independent physical benchmark source secured.
• Real bottleneck: behind “node nm / qubit count / TB/s” headlines, the actual rate-limiter is grid access (AI compute), data movement and software (memory/in-memory), economics (silicon), and cooling and demonstration (superconducting, thermodynamic).
• Quantum hype: 2026 prediction markets are near-unanimously skeptical of a practical, retail quantum product within the year — consistent with the firm’s logical-compiler thread, where compiler progress does not equal hardware demonstration.

7. What to watch

1. AI compute: whether grid-interconnection queues (4–10 yrs) shorten, and whether SMR/microreactor pilots move from criticality to commercial datacenter generation (HALEU fuel supply is the gate).
2. Silicon economics: whether chiplets and advanced packaging offset the rising per-transistor cost, and where HBM4/hybrid-bonding yield and heat halt scaling.
3. In-memory: whether the software ecosystem (not device physics) matures enough for digital CNM to move beyond niches; analog CIM remains research-stage.
4. Post-CMOS: the physical-qubit count and time from below-threshold QEC (Λ = 2.14) to a useful FT computation; and whether any thermodynamic claim earns an independent physical benchmark.

References

• Google Quantum AI. 2024. “Quantum error correction below the surface code threshold.” Nature. https://www.nature.com/articles/s41586-024-08449-y
• Gholami, Amir, et al. 2024. “AI and Memory Wall” (compute-in/near-memory; data-movement energy). arXiv:2401.14428. https://arxiv.org/abs/2401.14428
• Photonic neuromorphic computing review. 2024. Nature Reviews Electrical Engineering. https://www.nature.com/articles/s44287-024-00050-9
• World Economic Forum. 2025. AI compute and grid-interconnection timelines (secondary/high).
• TSMC N2 node and roadmap; process-node naming (secondary/high) — Wikipedia, SemiWiki.
• Modha, Dharmendra S., et al. 2023. IBM NorthPole. Science (adh1174) — energy efficiency vs. 12nm GPU (primary/high).
• SeeQC on-chip SFQ control, gate fidelity >99.5% (2026-03) — vendor / The Quantum Insider (secondary/med).
• Thermodynamic/reversible (Extropic, Normal Computing) efficiency claims — Tom’s Hardware (secondary/low); vendor simulation and toy benchmarks, no independent physical benchmark secured.

Source knowledge asset: knowledge-base/deep-dives/computing-power/part0-landscape.md (generated 2026-07-07, VERIFIED — 3-vote adversarial verification, 9 synthesized findings confirmed, 2 killed, 0 unverified). This draft inherits the figures and source attributions of the original and creates no new figures or sources.

Disclosure

This post is for information only and is not investment advice. The author holds no position in, and no financial interest in, the listed companies mentioned (TSMC, Intel INTC, IBM, Micron MU, SK Hynix, Samsung, ASML, and others).

COI note: This document describes listed and private computing/semiconductor companies (TSMC, Intel, IBM, Micron, SK Hynix, Samsung, ASML, SeeQC, UPMEM, Extropic, Normal Computing and others) in a factual, neutral technology/roadmap context. There is no buy/sell implication. Vendor efficiency multiples and roadmap dates are all attributed as “vendor/author/preprint claims (projections)” and are not mutually comparable across differing assumptions.